Increasing density in chip design is a mixed blessing: fabrication costs can be lowered, but increased wire-routing congestion can offset those gains. This is already a significant problem at the 90-nanometer level, and promises only to get worse at smaller geometries. Pre-implementation analysis can identify potential hot spots and allow for synthesis optimization, as well as adjustments to physical and floor-plan constraints and register transfer levels. This can, in turn, save both time and effort. Congestion becomes an issue at the place-and-route phase of design, if too many wires must run through the same regions. Routing tools visualize the design as a two-dimensional array with a maximum number of wire-routing tracks per grid. Congestion is defined as track demand exceeding supply. The two main sources are physical constraints and logical, or standard-cell, congestion. That is, depending on the logical processes involved, some netlists will have more highly interconnected topologies. A given combination of these constraints can lead to design rule check and timing violations, making a design unroutable or only 'difficult to route.' In either case, additional modifications can add weeks to a project schedule. Extrapolating from known 90-nm congestion issues can offer a sense of the challenges at the 45-nm level. For example, 33 percent congestion at the larger die size can translate into 80 percent congestion at the smaller. Without a better means of avoiding congestion, 45-nm design will likely demand significantly more resources.