To meet the expanding need for improved manufacturing technologies that target smaller, faster, and cost-efficient consumer electronics, device stacking and wafer-level packaging technologies have emerged to allow fabrication and testing on wafer-level before dicing and assembling and to enable new technologies. Topics covered are 3D chip stacking, advanced packaging, wafer-to-wafer alignment, and 3D interconnects. With device stacking based on aligned wafer bonding, two processed wafers are aligned and bonded face-to-face. Various described chip fabrication processes result in a functional density, a minimized device, and smaller packages dimensions. In contrast to heterogeneous subsystems such as CMOS or microelectromechanical sensors/systems (MEMS), which can require disparate and non-compatible processing steps, aligned wafer bonding permits processing of different functional subsystems on separate wafers. This technology permits increasing levels of integration that result in better performance and functionality while lowering cost, shrinking size, and reducing weight and power consumption. For advanced packaging, bond pad arrays with pitch under 40 mu m are on the drawing board, and for wafer to wafer alignment, SmartView face to face alignment permits alignment keys of both wafers inside the bond interface. The most effective investigated wafer bonding techniques for 3D interconnects applications are Cu-Cu diffusion bonding and adhesive bonding with BCB.